1. Field of Invention
The present invention relates to a pixel structure. More particularly, the present invention relates to a pixel structure capable of raising the ratio of on-state/off-state current (Ion/Ioff) effectively.
2. Description of Related Art
Thanks to the progress of semiconductor elements and display devices, multimedia technology has been highly developed and adopted nowadays. For display devices, thin film transistor liquid crystal display (TFT-LCD), having the advantages of high picture quality, excellent space utilization, low power consumption, non-radiation, etc., has gradually become the mainstream in the market.
An ordinary TFT-LCD mainly includes a thin film transistor array substrate (TFT array substrate), a color filter substrate, and a liquid crystal layer disposed between the above two substrates. The TFT array substrate is constituted by a substrate, TFTs and pixel electrodes arranged on the substrate in an array, scan lines, and data lines. In general, the scan line and the data line can transmit signals to the corresponding TFT for the purpose of displaying.
In LCDs of high resolution and high vertical scan frequency, the TFT array should meet the demand of a high Ion/Ioff ratio. Generally, only when the Ion/Ioff ratio is not less than 105, can the TFT-LCD provide a preferable display quality.
In view of the above, there are two methods for increasing the Ion/Ioff ratio in the prior art: (1) increasing the on-state current (Ion); (2) reducing the off-state current (Ioff). According to the first method, the on-state current is set by adjusting the ratio of width/length of channel (W/L of channel) of TFT. However, if the width of channel of TFT is continuously enlarged, a large gate-drain parasitic capacitance (Cgd) and kick-back voltage may be generated, thus causing the problem of flickering and affecting the display quality.
The second method is employed by reducing the off-state current, which does not have the above-described disadvantages. In other words, the leakage current phenomenon occurred in the TFT can be reduced and the Ion/Ioff ratio can be effectively increased without causing a large Cgd and kick-back voltage. It should be noted that the aforementioned leakage current phenomenon is mainly caused by a non-completely etched ohmic contact layer in the semiconductor layer.
FIG. 1 is a schematic top view of a conventional pixel structure. FIG. 1A is a schematic sectional view along the line A-A′ of FIG. 1. Referring to FIGS. 1 and 1A, the pixel structure 300 includes a TFT 100 and a pixel electrode 200, and the TFT 100 is driven by the scan line 170 and the data line 180 on the substrate 160. The TFT 100 includes a gate 110, a gate insulation layer 120, a semiconductor layer 130, a source 140a, a drain 140b, and a protection layer 150. The gate 110 is electrically connected to the scan line 170. The gate insulation layer 120 covers the gate 110 and the scan line 170. The semiconductor layer 130 is disposed on the gate insulation layer 120 over the gate 110, and the semiconductor layer 130 is composed of a channel layer 130a and an ohmic contact layer 130b. The source 140a and the drain 140b are disposed on the semiconductor layer 130, and the source 140a is electrically connected to the data line 180. The protection layer 150 covers the source 140a and the drain 140b, and a contact hole 150a is disposed therein for exposing the drain 140b. The pixel electrode 200 is electrically connected to the drain 140b of the TFT 100.
Referring to FIG. 1A again, an ordinary TFT process often employs a photoresist layer (not shown), the source 140a, and the drain 140b as an etching mask to remove the ohmic contact layer 130b above the gate 110, i.e., the TFT 100 is fabricated by back channel etching (BCE). However, when the method is used in fabricating a large-sized panel, as the uniformity of the overall etching speed differs, a part of the ohmic contact layer 130b may be left near the region 190 as shown in FIG. 1 or FIG. 1A. As the ohmic contact layer 130b has a good conductive property, the leakage current may occur along the path A as shown in FIG. 1. Therefore, the pixel electrode 200 cannot keep the data voltage applied thereto, thus causing poor display quality such as flickering or cross talk.
There are three conventional methods for reducing the above-mentioned leakage current phenomenon. The first method increases the interlayer distance between the semiconductor layer 130, the source 140a, and the drain 140b. Referring to FIG. 2, the second method enlarges the width w of the cutout 195 of the semiconductor layer 130 between the source 140a and the drain 140b, such that the leakage current cannot be circulated in the path B easily. However, the above two methods may increase the load capacitance of the circuit and reduce the aperture ratio of the pixel structure 300, thus causing distortion or flickering of the driving signal.
Referring to FIG. 3, the third method increases the distance between the source 140a and the drain 140b at the edge, which is disclosed by U.S. No. 20050041169. As shown in FIG. 3, the distance between the source 140a and the drain 140b is L1 (i.e., length of the channel), and the distance between the edges of source 140a and the drain 140b is L2. That is to say, the distance between the source 140a and the drain 140b at the edge is increased by ΔL, and the width is changed by Δw. Therefore, by this design, the occurrence of leakage current can be reduced without decreasing the on-state current. However, the design can neither be used to reduce the leakage current phenomenon caused by the non-uniform dry etching of the ohmic contact layer 130b, nor to raise the Ion/Ioff ratio to the required level.